/*****************************************************************************\ * * Filename: wnvhw.h * * Description: This header defines the board physical port addresses, * logical port number, logical to physical port address * conversion macros and any hardware related mappings. * * * Original author: Alice Kao * * Copyright (c) Winnov L.P., 1996 * All Rights Reserved. * * \*****************************************************************************/ #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ #ifndef WNVHW_H #define WNVHW_H /*****************************************************************************/ /* PUBLIC DEFINES and ENUMERATIONS */ #define WNVHW_AVI_PORT_NUM 32 #define WNVHW_AVI_PORT_OFFSET 0x400 #define WNVHW_PNP_AVI_PORT_OFFSET 0x4 #define WNVHW_MPLUG_AVI_PORT_OFFSET 0x1 #define WNVHW_PCI_AVI_PORT_OFFSET 0x1 #define WNVHW_IO_PORT_TYPES 2 // right now CFG and AVI #define WNVHW_MAX_BOARDS 10 /* total boards per system */ #define WNVHW_MAX_PORT_BASE 4 // including no base range. Just // so we have a consistent index base #define WNVHW_MPLUG_HOSTPORT_NUM 4 // // Chip identification in MMA, bit 0-5 of MMA #define WNVHW_CHIP_ID_MASK 0x3F enum WAVI_VERSION { WNVHW_WAVI1 = 0x02, /* The original Samsung */ WAVI_VERSION_WAVI1 = 0x02, WNVHW_WAVI95 = 0x12, /* Hundai part with line avg during Huffman fix */ WAVI_VERSION_WAVI95 = 0x12, WNVHW_WAVI97 = 0x22, WAVI_VERSION_WAVI97 = 0x22, WNVHW_WIMP = 0x03, WAVI_VERSION_WIMP = 0x03, }; // // Physical port address // #define WNVHW_PRICONFIGPORT 0x5A04 #define WNVHW_ALTCONFIGPORT 0x5A05 #define WNVHW_PRIPORTBASE1 0x0160 #define WNVHW_PRIPORTBASE2 0x0150 #define WNVHW_PRIPORTBASE3 0x0140 #define WNVHW_ALTPORTBASE1 0x0120 #define WNVHW_ALTPORTBASE2 0x0110 #define WNVHW_ALTPORTBASE3 0x0100 // CFG register for media-plug #define WNVHW_MPLUGCONFIGPORT 0x0036 #define WNVHW_MPLUGCONFIGVAL 0x3 // hard coded config value for mplug // // Configuration board type // #define WNVHW_PRIMARY 0 #define WNVHW_ALTERNATE 1 // // Base port select values. These are // the value to be set in the configuration port // For ISA // #define WNVHW_NO_BASE_RANGE 0x0000 #define WNVHW_BASE_RANGE_1 0x0001 #define WNVHW_BASE_RANGE_2 0x0002 #define WNVHW_BASE_RANGE_3 0x0003 // // Generic logical AVI port address. It will // be translated into the physical port address // enum WAVI_REG { WNVHW_PORT_HST1PTR =0x0000, WNVHW_PORT_HST2PTR =0x0001, WNVHW_PORT_SPLPTR =0x0002, WNVHW_PORT_AUDPTR =0x0003, WNVHW_PORT_VID1PTR =0x0004, WNVHW_PORT_MXRPTR =0x0005, WNVHW_PORT_VID2PTR =0x0006, WNVHW_PORT_MXWPTR =0x0007, WNVHW_PORT_HST1DAT =0x0008, WNVHW_PORT_HST2DAT =0x0009, WNVHW_PORT_RLDPTR1 =0x000A, WNVHW_PORT_RLDPTR2 =0x000B, WNVHW_PORT_MMA =0x000C, WNVHW_PORT_CTL =0x000D, WNVHW_PORT_ISR =0x000E, WNVHW_PORT_ITR =0x000F, WNVHW_PORT_ATTN =0x0010, WNVHW_PORT_GAIN =0x0011, WNVHW_PORT_FREQ =0x0012, WNVHW_PORT_4C00 =0x0013, WNVHW_PORT_AUDMIX1 =0x0014, WNVHW_PORT_AUDMIX2 =0x0015, WNVHW_PORT_5800 =0x0016, WNVHW_PORT_5C00 =0x0017, WNVHW_PORT_VOF =0x0018, WNVHW_PORT_VCT =0x0019, WNVHW_PORT_6800 =0x001A, WNVHW_PORT_CTL2 =0x001A, // WIMP WNVHW_PORT_6C00 =0x001B, WNVHW_PORT_CTLL =0x001C, WNVHW_PORT_7400 =0x001D, WNVHW_PORT_BANKSEL =0x001D, // WIMP WNVHW_PORT_7800 =0x001E, WNVHW_PORT_I2C =0x001E, // WIMP WNVHW_PORT_TSTMODE =0x001F, }; // MMA Register #define WNVHW_NWDBIT 0x8000 /* NOWS Write Disable */ #define WNVHW_NRDBIT 0x4000 /* NOWS Read Disable */ #define WNVHW_MMAFIELD 0x3E00 /* Memory Map Address */ #define WNVHW_MMEBIT 0x0100 /* Memory Map Enable */ #define WNVHW_FMFIELD 0x00C0 /* FM config, Read only */ #define WNVHW_DSSFIELD 0x0030 /* Disney Sound Source config, Read Only */ #define WNVHW_CVXFIELD 0x000C /* CoVoX speech thing config, Read Only */ #define WNVHW_REVFIELD 0x0003 /* WAVIA ASIC Revision, Read Only */ #define WNVHW_AVGCENBIT 0x8000 /* W97 and later: Average Chroma Enable */ #define WNVHW_AUDXSEL_INT97 0x4000 /* W97: Crystal selection is internal (using IMI bit) */ #define WNVHW_AUDXSEL 0x4000 /* WIMP: Crystal selection (replaces IMI bit) */ #define WNVHW_CS4218BIT 0x2000 /* W97 and later: 4218 codec configuration */ #define WNVHW_VDECODESEL 0x1000 /* W97 and later: Video decoder select for inverted polarity */ #define WNVHW_BANKSEL 0x0800 /* W97 and later: to enable the memory chip select */ #define WNVHW_DHYYY 0x0400 /* W97 and later: Luma only Delta Huffman */ #define WNVHW_DHRES 0x0200 /* W97 and later: Delta Huffman Residual alogorithm */ #define WNVHW_DHRND 0x0100 /* W97 and later: Delta Huffman Rounding algorithm */ #define WNVHW_MEDREN 0x0080 /* W97 and later: Median Filter Return Effect */ #define WNVHW_VIDVCI 0x0040 /* W97 and later: DVCI video format */ #define WNVHW_VERSIONFIELD 0x0030 /* W95 and later: Read Only Version */ #define WNVHW_WAVIIDFIELD 0x000F /* All Versions: WAVI ASIC Revision, Read Only */ #define WNVHW_FULLID 0x003F /* completely identify the chip version... W95 and above! */ // CTL Register #define WNVHW_VSEBIT 0x8000 /* Video Sampler Enable */ #define WNVHW_VSTBIT 0x4000 /* Video Status */ #define WNVHW_VSSBIT 0x2000 /* Video Source Select */ #define WNVHW_VSCBIT 0x1000 /* Video Source Component(1)/Composite(0) */ #define WNVHW_RGBBIT 0x0800 /* RGB(1)/YUV(0) Video Space */ #define WNVHW_VFSFIELD 0x0700 /* Video Filter Select */ #define WNVHW_VFSFIELD_NONE 0x0000 /* Bypass filters */ #define WNVHW_VFSFIELD_MED3 0x0100 /* 3 tap median filter */ #define WNVHW_VFSFIELD_FIR2 0x0200 /* 2 pix FIR filter */ #define WNVHW_VFSFIELD_BOTH2 0x0300 /* Median and 2 pix FIR */ #define WNVHW_VFSFIELD_MED4 0x0400 /* 4 pix FIR filter */ #define WNVHW_VFSFIELD_BOTH4 0x0500 /* Median and 4 pix FIR */ #define WNVHW_VFSFIELD_MED8 0x0600 /* 8 pix FIR filter */ #define WNVHW_VFSFIELD_BOTH8 0x0700 /* Median and 8 pix FIR filter */ #define WNVHW_VDFFIELD 0x00E0 /* Video Data Capture Format */ #define WNVHW_VDFFIELD_DYCQ 0x0000 /* DYCQ */ #define WNVHW_VDFFIELD_YCQ 0x0020 /* YCQ */ #define WNVHW_VDFFIELD_YCH 0x0040 /* YCH */ #define WNVHW_VDFFIELD_RGB 0x0060 /* RGB */ #define WNVHW_VDFFIELD_DH4 0x0080 /* DH4 */ #define WNVHW_VDFFIELD_DH5 0x00A0 /* DH5 */ #define WNVHW_VDFFIELD_DH6 0x00C0 /* DH6 */ #define WNVHW_VDFFIELD_DH7 0x00E0 /* DH7 */ #define WNVHW_CTLBIT4 0x0010 /* not used */ #define WNVHW_I2CBIT 0x0008 /* I2C Bus Clock */ #define WNVHW_IMIBIT 0x0004 /* IM-Bus Identify */ #define WNVHW_IMCBIT 0x0002 /* IM-Bus Clock */ #define WNVHW_IMDBIT 0x0001 /* IM-Bus Data */ /* WIMP variation */ #define WNVHW_SCL 0x0008 /* WIMP: I2C bus clock */ #define WNVHW_PIXGEN 0x0004 /* WIMP: pixel generator */ #define WNVHW_PXCCD 0x0002 /* WIMP: Pixel Genreator CCD Mode enable */ #define WNVHW_SDA 0x0001 /* WIMP: I2C bus data */ // CTL2 Register (WIMP ONLY) #define WNVHW_CCLKEN 0x8000 //Enable CCLK #define WNVHW_VCLK_INV 0x4000 //Invert VCLK #define WNVHW_DPLL_EN 0x2000 //Digital PLL enable #define WNVHW_VCPHASE 0x1000 //Vclock Phase control #define WNVHW_VCLK_EN 0x0C00 //Vclock source selection #define WNVHW_VCLK_EN_GND 0x0C00 //00 for ground #define WNVHW_VCLK_EN_MOV2 0x0400 // Mclock/2 #define WNVHW_VCLK_EN_VEXT 0x0800 // External Vclock #define WNVHW_VCLK_EN_MCLK 0x0C00 // MClock #define WNVHW_MCLK_EN 0x0300 //Mclock source selection #define WNVHW_MCLK_EN_GND 0x0300 //00 for ground #define WNVHW_MCLK_EN_GND2 0x00 //00 for ground (reversed already!) #define WNVHW_MCLK_EN_COV2 0x0100 // CCD clock/2 #define WNVHW_MCLK_EN_AUD 0x0200 // Audio clock #define WNVHW_MCLK_EN_CCLK 0x0300 // CCD Clock #define WNVHW_GPIO2_OE 0x0080 //GPIO 2 OE #define WNVHW_GPIO1_OE 0x0040 //GPIO 1 OE #define WNVHW_GPIO0_OE 0x0020 //GPIO 0 OE #define WNVHW_GPIO4 0x0010 //GPIO 4 = RST_OUT #define WNVHW_GPIO3 0x0008 //GPIO 3 #define WNVHW_GPIO2 0x0004 //GPIO 2 #define WNVHW_GPIO1 0x0002 //GPIO 1 #define WNVHW_GPIO0 0x0001 //GPIO 0 // Interrupt register ISR/ITR bit mask #define WNVHW_VIEBIT 0x8000 /* Video Interrupt Enable */ #define WNVHW_VI2BIT 0x4000 /* Video Interrupt 1, Read Only */ #define WNVHW_VI1BIT 0x2000 /* Video Interrupt 2, Read Only */ #define WNVHW_AIEBIT 0x1000 /* Audio Interrupt Enable */ #define WNVHW_AISFIELD 0x0C00 /* Audio Interrupt Status, Read Only */ #define WNVHW_AISFIELD_NOINT 0x0000 /* no audio interrupt */ #define WNVHW_AISFIELD_1INT 0x0400 /* one audio interrupt */ #define WNVHW_AISFIELD_OVERRUN 0x0800 /* audio overrun */ #define WNVHW_AISFIELD_2INT 0x0C00 /* two audio interrupts */ #define WNVHW_FIEBIT 0x0200 /* FM Interrupt Enable */ #define WNVHW_FMIBIT 0x0100 /* FM Interrupt, Read Only */ #define WNVHW_SIEBIT 0x0080 /* SCSI Interrupt Enable */ #define WNVHW_SCIBIT 0x0040 /* SCSI Controller Interrupt, Read Only */ #define WNVHW_CIEBIT 0x0020 /* Control-L Interrupt Enable */ #define WNVHW_CLIBIT 0x0010 /* Control-L Interrupt, Read Only */ #define WNVHW_IDTBIT 0x0008 /* Interrupt Detect, Read Only */ #define WNVHW_ITMBIT WNVHW_IDTBIT /* Interrupt test mode, Write Only */ #define WNVHW_ISELFIELD 0x0007 /* Interrupt Select */ #define WNVHW_ISELFIELD_NONE 0x0000 /* Interrupts disconnected */ #define WNVHW_ISELFIELD_IRQ2 0x0001 /* IRQ2 */ #define WNVHW_ISELFIELD_IRQ5 0x0002 /* IRQ5 was reversed with 7*/ #define WNVHW_ISELFIELD_IRQ7 0x0003 /* IRQ7 was reversed with 5 */ #define WNVHW_ISELFIELD_IRQ10 0x0004 /* IRQ10*/ #define WNVHW_ISELFIELD_IRQ11 0x0005 /* IRQ11*/ #define WNVHW_ISELFIELD_IRQ12 0x0006 /* IRQ12*/ #define WNVHW_ISELFIELD_IRQ15 0x0007 /* IRQ15*/ // Audio ATTN // 4216 (and ASCO) format of the upper 12 bits: #define WNVHW_ATTN_MASK 0x0FFF /* mask of useable bits */ #define WNVHW_UNUSEDFIELD 0xF000 /* not used */ #define WNVHW_ATTLFFIELD 0x0F00 /* Left Output Channel Attenuation, Write Only */ #define WNVHW_ATTRTFIELD 0x00F0 /* Right Output Channel Attenuation, Write Only */ // 4218 format of the upper 12 bits: #define WNVHW_4218_ATTLFFIELD 0x3E00 /* 4218: 5 bit Left Output Channel Attenuation, Write Only */ #define WNVHW_4218_ATTRTFIELD 0x01F0 /* 4218: 5 bit Right Output Channel Attenuation, Write Only */ // common between 4216 and 4218 #define WNVHW_ASS2FIELD 0x000C /* Audio Source Select, Write Only */ #define WNVHW_ASS2FIELD_VID1 0x0000 #define WNVHW_ASS2FIELD_MIC 0x0004 #define WNVHW_ASS2FIELD_VID2 0x0008 #define WNVHW_ASS2FIELD_LINE 0x000C #define WNVHW_AFSBIT 0x0002 /* Audio freq select (SPAM only) 0=22.5792,1=24.576 */ #define WNVHW_AXEBIT 0x0001 /* Audio expansion enable */ // Audio GAIN #define WNVHW_MUTBIT 0x0400 /* Mute, Write Only */ #define WNVHW_ISLBIT 0x0200 /* Input Select Left channel, Write Only */ /* 0=LIN1, 1=IN2 (ASS2) */ #define WNVHW_ISRBIT 0x0100 /* Input Select Right channel, Write Only */ /* 0=LIN1, 1=IN2 (ASS2) */ #define WNVHW_GAINLFFIELD 0x00F0 /* Left Input Channel Gain, Write Only */ #define WNVHW_GAINRTFIELD 0x000F /* Right Input Channel Gain, Write Only */ // Audio FREQ #define WNVHW_AOVFIELD 0xFF00 /* Audio Output Volume */ #define WNVHW_ACEBIT 0x0080 /* Audio Converter Enable */ #define WNVHW_APEBIT 0x0040 /* Audio Phase Error */ #define WNVHW_AMSBIT 0x0020 /* Audio Mode Stereo */ #define WNVHW_ADDBIT 0x0010 /* Audio Digital Port Data */ #define WNVHW_FREQFIELD 0x000F /* Audio Frequency */ #define WNVHW_FREQFIELD_44100 0x0001 #define WNVHW_FREQFIELD_29400 0x0002 #define WNVHW_FREQFIELD_22050 0x0003 #define WNVHW_FREQFIELD_14700 0x0005 #define WNVHW_FREQFIELD_11025 0x0007 #define WNVHW_FREQFIELD_08820 0x0009 #define WNVHW_FREQFIELD_07350 0x000B // Audio MIX 1/2 #define WNVHW_MIXRFIELD 0xFF00 /* Right channel output volume */ #define WNVHW_MIXLFIELD 0x00FF /* Left channel output volume */ // Video Offset #define WNVHW_VOFCRFIELD 0xF000 /* Video Offset Chroma Red */ #define WNVHW_VOFCBFIELD 0x0F00 /* Video Offset Chroma Blue */ #define WNVHW_VOFYFIELD 0x00F0 /* Video Offset Luma */ #define WNVHW_GBCBIT 0x0008 /* Video Input Gray to Binary on Chroma */ #define WNVHW_GBYBIT 0x0004 /* Video Input Gray to Binary on Luma */ #define WNVHW_VSPBIT 0x0002 /* Video Input VSP Enable */ #define WNVHW_VSDBIT 0x0001 /* Video Input VSD Detect, Read Only */ // Video Contrast Reg #define WNVHW_VCTCRFIELD 0xF000 /* Cr contrast */ #define WNVHW_VCTCBFIELD 0x0F00 /* Cb Contrast */ #define WNVHW_VCTYFIELD 0x00F0 /* Y Contrast */ #define WNVHW_VHSDFIELD 0x000F /* Video Horizontal Synch Delay */ // Control-L Reg #define WNVHW_STRBIT 0x8000 /* Control-L Start bit */ #define WNVHW_TRGBIT 0x4000 /* Control-L Trigger Send */ #define WNVHW_ARMBIT 0x2000 /* Control-L Armed, Read Only */ #define WNVHW_VVSBIT 0x1000 /* Video Vert Synch, Read Only */ #define WNVHW_CLDBIT 0x0800 /* Control-L Direct Data */ #define WNVHW_E2BIT 0x0400 /* TBD */ #define WNVHW_E1BIT 0x0200 /* TBD */ #define WNVHW_E0BIT 0x0100 /* TBD */ #define WNVHW_CLDATA 0x00FF /* Control L Data */ // SRAM breakdown size #define WNVHW_AUDIO_HALF_BUF_SIZE 0x01000 #define WNVHW_AUDIO_BUF_SIZE 0x02000 #define WNVHW_CPB_SIZE 0x00100 #define WNVHW_CODE_BUF_SIZE 0x01000 // // SRAM virtual address location and size. // The address is a byte address and the // size is also in bytes. The hardware is // will figure out the proper translation // into the appropriate physical address. // #define WNVHW_SRAM_VIRTUAL_ADDR 0x10000 #define WNVHW_SRAM_SIZE_IN_BYTES 0x10000 // // defines for Plug and Play boards // //#define WNVHW_BOARD0_ID "CTL0039" #define WNVHW_PNP_VIDEUM1 "WNV0001" #define WNVHW_MEDIA_PLUG1 "WNV0002" #define WNVHW_PNP_VIDEUM1_BYTE_LEN 128 #define WNVHW_MEDIA_PLUG1_BYTE_LEN 8 // 3 ports + 1 data alias port // // Videum AV PCI board information // #define WNVHW_AV_PCI_VENDER_ID 0x1095 #define WNVHW_AV_PCI_DEVICE_ID 0x0647 #endif // WNVHW.h #ifdef __cplusplus } #endif /********** END OF FILE ************************************/