/////////////////////////////////////////////////////////////////////////////// // Copyright (c) Winnov L.P., 1997. All rights reserved. // common.h /////////////////////////////////////////////////////////////////////////////// #ifndef _COMMON_INCLUDED #define _COMMON_INCLUDED #ifdef WINKERNEL // WDM // comment out to allow dependencies to update...include #define _loadds #define NEARPTR DWORD typedef UINT VERSION; #else #include #include #ifdef WIN32 #define NEARPTR DWORD #else #define NEARPTR WORD #endif #endif typedef void *PVOID; #define TRAP #define SAMPLERATE 48000 extern DWORD MyGetTime (void); #define AUDIOBUFFERBASE 0x10000 // from constant.h #define NBOARDS 2 /* !!! define this elsewhere */ #define BOARDN 0 /* the board number */ #define DEF_SAMPLERATE 8000 #define DRIFT_TIME 12 /* drift time allocation in millisec */ #define READ_DRIFT_TIME (DRIFT_TIME/2) #define POLL_TIME 34 #define MAXPOLLTIME 20 #define MINPOLLTIME 5 #define WAVI_AUDIOBUFFERSIZE 8192L // map hardware defines universally #ifdef WINKERNEL #include "wnvhw.h" #define HW_PORT_HST1PTR WNVHW_PORT_HST1PTR #define HW_PORT_HST2PTR WNVHW_PORT_HST2PTR #define HW_PORT_SPLPTR WNVHW_PORT_SPLPTR #define HW_PORT_AUDPTR WNVHW_PORT_AUDPTR #define HW_PORT_VID1PTR WNVHW_PORT_VID1PTR #define HW_PORT_MXRPTR WNVHW_PORT_MXRPTR #define HW_PORT_VID2PTR WNVHW_PORT_VID2PTR #define HW_PORT_MXWPTR WNVHW_PORT_MXWPTR #define HW_PORT_HST1DAT WNVHW_PORT_HST1DAT #define HW_PORT_HST2DAT WNVHW_PORT_HST2DAT #define HW_PORT_RLDPTR1 WNVHW_PORT_RLDPTR1 #define HW_PORT_RLDPTR2 WNVHW_PORT_RLDPTR2 #define HW_PORT_MMA WNVHW_PORT_MMA #define HW_PORT_CTL WNVHW_PORT_CTL #define HW_PORT_ISR WNVHW_PORT_ISR #define HW_PORT_ITR WNVHW_PORT_ITR #define HW_PORT_ATTN WNVHW_PORT_ATTN #define HW_PORT_GAIN WNVHW_PORT_GAIN #define HW_PORT_FREQ WNVHW_PORT_FREQ #define HW_PORT_4C00 WNVHW_PORT_4C00 #define HW_PORT_AUDMIX1 WNVHW_PORT_AUDMIX1 #define HW_PORT_AUDMIX2 WNVHW_PORT_AUDMIX2 #define HW_PORT_5800 WNVHW_PORT_5800 #define HW_PORT_5C00 WNVHW_PORT_5C00 #define HW_PORT_VOF WNVHW_PORT_VOF #define HW_PORT_VCT WNVHW_PORT_VCT #define HW_PORT_6800 WNVHW_PORT_6800 #define HW_PORT_CTL2 WNVHW_PORT_CTL2 #define HW_PORT_6C00 WNVHW_PORT_6C00 #define HW_PORT_CTLL WNVHW_PORT_CTLL #define HW_PORT_7400 WNVHW_PORT_7400 #define HW_PORT_BANKSEL WNVHW_PORT_BANKSEL #define HW_PORT_7800 WNVHW_PORT_7800 #define HW_PORT_I2C WNVHW_PORT_I2C #define HW_PORT_TSTMODE WNVHW_PORT_TSTMODE // MMA Register #define HW_NWDBIT WNVHW_NWDBIT /* NOWS Write Disable */ #define HW_NRDBIT WNVHW_NRDBIT /* NOWS Read Disable */ #define HW_MMAFIELD WNVHW_MMAFIELD /* Memory Map Address */ #define HW_MMEBIT WNVHW_MMEBIT /* Memory Map Enable */ #define HW_FMFIELD WNVHW_FMFIELD /* FM config, Read only */ #define HW_DSSFIELD WNVHW_DSSFIELD /* Disney Sound Source config, Read Only */ #define HW_CVXFIELD WNVHW_CVXFIELD /* CoVoX speech thing config, Read Only */ #define HW_REVFIELD WNVHW_REVFIELD /* WAVIA ASIC Revision, Read Only */ #define HW_AVGCENBIT WNVHW_AVGCENBIT /* W97 and later: Average Chroma Enable */ #define HW_AUDXSEL_INT97 WNVHW_AUDXSEL_INT97 /* W97: Crystal selection is internal (using IMI bit) */ #define HW_AUDXSEL WNVHW_AUDXSEL /* WIMP: Crystal selection (replaces IMI bit) */ #define HW_CS4218BIT WNVHW_CS4218BIT /* W97 and later: 4218 codec configuration */ #define HW_VDECODESEL WNVHW_VDECODESEL /* W97 and later: Video decoder select for inverted polarity */ #define HW_BANKSEL WNVHW_BANKSEL /* W97 and later: to enable the memory chip select */ #define HW_DHYYY WNVHW_DHYYY /* W97 and later: Luma only Delta Huffman */ #define HW_DHRES WNVHW_DHRES /* W97 and later: Delta Huffman Residual alogorithm */ #define HW_DHRND WNVHW_DHRND /* W97 and later: Delta Huffman Rounding algorithm */ #define HW_MEDREN WNVHW_MEDREN /* W97 and later: Median Filter Return Effect */ #define HW_VIDVCI WNVHW_VIDVCI /* W97 and later: DVCI video format */ #define HW_VERSIONFIELD WNVHW_VERSIONFIELD /* W95 and later: Read Only Version */ #define HW_WAVIIDFIELD WNVHW_WAVIIDFIELD /* All Versions: WAVI ASIC Revision, Read Only */ #define HW_FULLID WNVHW_FULLID /* completely identify the chip version... W95 and above! */ // // Chip identification in MMA #define HW_CHIP_ID_MASK WNVHW_CHIP_ID_MASK #define HW_WAVI1 WNVHW_WAVI1 /* The original Samsung */ #define HW_WAVI95 WNVHW_WAVI95 /* Hundai part with line avg during Huffman fix */ #define HW_WAVI97 WNVHW_WAVI97 #define HW_WIMP WNVHW_WIMP // CTL Register #define HW_VSEBIT WNVHW_VSEBIT /* Video Sampler Enable */ #define HW_VSTBIT WNVHW_VSTBIT /* Video Status */ #define HW_VSSBIT WNVHW_VSSBIT /* Video Source Select */ #define HW_VSCBIT WNVHW_VSCBIT /* Video Source Component(1)/Composite(0) */ #define HW_RGBBIT WNVHW_RGBBIT /* RGB(1)/YUV(0) Video Space */ #define HW_VFSFIELD WNVHW_VFSFIELD /* Video Filter Select */ #define HW_VFSFIELD_NONE WNVHW_VFSFIELD_NONE /* Bypass filters */ #define HW_VFSFIELD_MED3 WNVHW_VFSFIELD_MED3 /* 3 tap median filter */ #define HW_VFSFIELD_FIR2 WNVHW_VFSFIELD_FIR2 /* 2 pix FIR filter */ #define HW_VFSFIELD_BOTH2 WNVHW_VFSFIELD_BOTH2 /* Median and 2 pix FIR */ #define HW_VFSFIELD_MED4 WNVHW_VFSFIELD_MED4 /* 4 pix FIR filter */ #define HW_VFSFIELD_BOTH4 WNVHW_VFSFIELD_BOTH4 /* Median and 4 pix FIR */ #define HW_VFSFIELD_MED8 WNVHW_VFSFIELD_MED8 /* 8 pix FIR filter */ #define HW_VFSFIELD_BOTH8 WNVHW_VFSFIELD_BOTH8 /* Median and 8 pix FIR filter */ #define HW_VDFFIELD WNVHW_VDFFIELD /* Video Data Capture Format */ #define HW_VDFFIELD_DYCQ WNVHW_VDFFIELD_DYCQ /* DYCQ */ #define HW_VDFFIELD_YCQ WNVHW_VDFFIELD_YCQ /* YCQ */ #define HW_VDFFIELD_YCH WNVHW_VDFFIELD_YCH /* YCH */ #define HW_VDFFIELD_RGB WNVHW_VDFFIELD_RGB /* RGB */ #define HW_VDFFIELD_DH4 WNVHW_VDFFIELD_DH4 /* DH4 */ #define HW_VDFFIELD_DH5 WNVHW_VDFFIELD_DH5 /* DH5 */ #define HW_VDFFIELD_DH6 WNVHW_VDFFIELD_DH6 /* DH6 */ #define HW_VDFFIELD_DH7 WNVHW_VDFFIELD_DH7 /* DH7 */ #define HW_CTLBIT4 WNVHW_CTLBIT4 /* not used */ #define HW_I2CBIT WNVHW_I2CBIT /* I2C Bus Clock */ #define HW_IMIBIT WNVHW_IMIBIT /* IM-Bus Identify */ #define HW_IMCBIT WNVHW_IMCBIT /* IM-Bus Clock */ #define HW_IMDBIT WNVHW_IMDBIT /* IM-Bus Data */ /* WIMP variation */ #define HW_SCL WNVHW_SCL /* WIMP: I2C bus clock */ #define HW_PIXGEN WNVHW_PIXGEN /* WIMP: pixel generator */ #define HW_PXCCD WNVHW_PXCCD /* WIMP: Pixel Genreator CCD Mode enable */ #define HW_SDA WNVHW_SDA /* WIMP: I2C bus data */ // CTL2 Register (WIMP ONLY) #define HW_CCLKEN WNVHW_CCLKEN /*Enable CCLK*/ #define HW_VCLK_INV WNVHW_VCLK_INV /*Invert VCLK*/ #define HW_DPLL_EN WNVHW_DPLL_EN /*Digital PLL enable*/ #define HW_VCPHASE WNVHW_VCPHASE /*Vclock Phase control*/ #define HW_VCLK_EN WNVHW_VCLK_EN /*Vclock source selection*/ #define HW_VCLK_EN_GND WNVHW_VCLK_EN_GND /*00 for ground*/ #define HW_VCLK_EN_MOV2 WNVHW_VCLK_EN_MOV2 /* Mclock/2*/ #define HW_VCLK_EN_VEXT WNVHW_VCLK_EN_VEXT /* External Vclock*/ #define HW_VCLK_EN_MCLK WNVHW_VCLK_EN_MCLK /* MClock*/ #define HW_MCLK_EN WNVHW_MCLK_EN /*Mclock source selection */ #define HW_MCLK_EN_GND WNVHW_MCLK_EN_GND /*00 for ground*/ #define HW_MCLK_EN_GND2 WNVHW_MCLK_EN_GND2 /*00 for ground (reversed already!)*/ #define HW_MCLK_EN_COV2 WNVHW_MCLK_EN_COV2 /* CCD clock/2*/ #define HW_MCLK_EN_AUD WNVHW_MCLK_EN_AUD /* Audio clock*/ #define HW_MCLK_EN_CCLK WNVHW_MCLK_EN_CCLK /* CCD Clock*/ #define HW_GPIO2_OE WNVHW_GPIO2_OE /*GPIO 2 OE*/ #define HW_GPIO1_OE WNVHW_GPIO1_OE /*GPIO 1 OE*/ #define HW_GPIO0_OE WNVHW_GPIO0_OE /*GPIO 0 OE*/ #define HW_GPIO4 WNVHW_GPIO4 /*GPIO 4 = RST_OUT*/ #define HW_GPIO3 WNVHW_GPIO3 /*GPIO 3*/ #define HW_GPIO2 WNVHW_GPIO2 /*GPIO 2*/ #define HW_GPIO1 WNVHW_GPIO1 /*GPIO 1*/ #define HW_GPIO0 WNVHW_GPIO0 /*GPIO 0*/ // Interrupt register ISR/ITR bit mask #define HW_VIEBIT WNVHW_VIEBIT /* Video Interrupt Enable */ #define HW_VI2BIT WNVHW_VI2BIT /* Video Interrupt 1, Read Only */ #define HW_VI1BIT WNVHW_VI1BIT /* Video Interrupt 2, Read Only */ #define HW_AIEBIT WNVHW_AIEBIT /* Audio Interrupt Enable */ #define HW_AISFIELD WNVHW_AISFIELD /* Audio Interrupt Status, Read Only */ #define HW_AISFIELD_NOINT WNVHW_AISFIELD_NOINT /* no audio interrupt */ #define HW_AISFIELD_1INT WNVHW_AISFIELD_1INT /* one audio interrupt */ #define HW_AISFIELD_OVERRUN WNVHW_AISFIELD_OVERRUN /* audio overrun */ #define HW_AISFIELD_2INT WNVHW_AISFIELD_2INT /* two audio interrupts */ #define HW_FIEBIT WNVHW_FIEBIT /* FM Interrupt Enable */ #define HW_FMIBIT WNVHW_FMIBIT /* FM Interrupt, Read Only */ #define HW_SIEBIT WNVHW_SIEBIT /* SCSI Interrupt Enable */ #define HW_SCIBIT WNVHW_SCIBIT /* SCSI Controller Interrupt, Read Only */ #define HW_CIEBIT WNVHW_CIEBIT /* Control-L Interrupt Enable */ #define HW_CLIBIT WNVHW_CLIBIT /* Control-L Interrupt, Read Only */ #define HW_IDTBIT WNVHW_IDTBIT /* Interrupt Detect, Read Only */ #define HW_ITMBIT WNVHW_IDTBIT /* Interrupt test mode, Write Only */ #define HW_ISELFIELD WNVHW_ISELFIELD /* Interrupt Select */ #define HW_ISELFIELD_NONE WNVHW_ISELFIELD_NONE /* Interrupts disconnected */ #define HW_ISELFIELD_IRQ2 WNVHW_ISELFIELD_IRQ2 /* IRQ2 */ #define HW_ISELFIELD_IRQ5 WNVHW_ISELFIELD_IRQ5 /* IRQ5 was reversed with 7*/ #define HW_ISELFIELD_IRQ7 WNVHW_ISELFIELD_IRQ7 /* IRQ7 was reversed with 5 */ #define HW_ISELFIELD_IRQ10 WNVHW_ISELFIELD_IRQ10 /* IRQ10*/ #define HW_ISELFIELD_IRQ11 WNVHW_ISELFIELD_IRQ11 /* IRQ11*/ #define HW_ISELFIELD_IRQ12 WNVHW_ISELFIELD_IRQ12 /* IRQ12*/ #define HW_ISELFIELD_IRQ15 WNVHW_ISELFIELD_IRQ15 /* IRQ15*/ // Audio ATTN // 4216 (and ASCO) format of the upper 12 bits: #define HW_ATTN_MASK WNVHW_ATTN_MASK /* mask of useable bits */ #define HW_UNUSEDFIELD WNVHW_UNUSEDFIELD /* not used */ #define HW_ATTLFFIELD WNVHW_ATTLFFIELD /* Left Output Channel Attenuation, Write Only */ #define HW_ATTRTFIELD WNVHW_ATTRTFIELD /* Right Output Channel Attenuation, Write Only */ // 4218 format of the upper 12 bits: #define HW_4218_ATTLFFIELD WNVHW_4218_ATTLFFIELD /* 4218: 5 bit Left Output Channel Attenuation, Write Only */ #define HW_4218_ATTRTFIELD WNVHW_4218_ATTRTFIELD /* 4218: 5 bit Right Output Channel Attenuation, Write Only */ // common between 4216 and 4218 #define HW_ASS2FIELD WNVHW_ASS2FIELD /* Audio Source Select, Write Only */ #define HW_ASS2FIELD_VID1 WNVHW_ASS2FIELD_VID1 #define HW_ASS2FIELD_MIC WNVHW_ASS2FIELD_MIC #define HW_ASS2FIELD_VID2 WNVHW_ASS2FIELD_VID2 #define HW_ASS2FIELD_LINE WNVHW_ASS2FIELD_LINE #define HW_AFSBIT WNVHW_AFSBIT /* Audio freq select (SPAM only) 0=22.5792,1=24.576 */ #define HW_AXEBIT WNVHW_AXEBIT /* Audio expansion enable */ // Audio GAIN #define HW_MUTBIT WNVHW_MUTBIT /* Mute, Write Only */ #define HW_ISLBIT WNVHW_ISLBIT /* Input Select Left channel, Write Only */ /* 0=LIN1, 1=IN2 (ASS2) */ #define HW_ISRBIT WNVHW_ISRBIT /* Input Select Right channel, Write Only */ /* 0=LIN1, 1=IN2 (ASS2) */ #define HW_GAINLFFIELD WNVHW_GAINLFFIELD /* Left Input Channel Gain, Write Only */ #define HW_GAINRTFIELD WNVHW_GAINRTFIELD /* Right Input Channel Gain, Write Only */ // Audio FREQ #define HW_AOVFIELD WNVHW_AOVFIELD /* Audio Output Volume */ #define HW_ACEBIT WNVHW_ACEBIT /* Audio Converter Enable */ #define HW_APEBIT WNVHW_APEBIT /* Audio Phase Error */ #define HW_AMSBIT WNVHW_AMSBIT /* Audio Mode Stereo */ #define HW_ADDBIT WNVHW_ADDBIT /* Audio Digital Port Data */ #define HW_FREQFIELD WNVHW_FREQFIELD /* Audio Frequency */ #define HW_FREQFIELD_44100 WNVHW_FREQFIELD_44100 #define HW_FREQFIELD_29400 WNVHW_FREQFIELD_29400 #define HW_FREQFIELD_22050 WNVHW_FREQFIELD_22050 #define HW_FREQFIELD_14700 WNVHW_FREQFIELD_14700 #define HW_FREQFIELD_11025 WNVHW_FREQFIELD_11025 #define HW_FREQFIELD_08820 WNVHW_FREQFIELD_08820 #define HW_FREQFIELD_07350 WNVHW_FREQFIELD_07350 // Audio MIX 1/2 #define HW_MIXRFIELD WNVHW_MIXRFIELD /* Right channel output volume */ #define HW_MIXLFIELD WNVHW_MIXLFIELD /* Left channel output volume */ // Video Offset #define HW_VOFCRFIELD WNVHW_VOFCRFIELD /* Video Offset Chroma Red */ #define HW_VOFCBFIELD WNVHW_VOFCBFIELD /* Video Offset Chroma Blue */ #define HW_VOFYFIELD WNVHW_VOFYFIELD /* Video Offset Luma */ #define HW_GBCBIT WNVHW_GBCBIT /* Video Input Gray to Binary on Chroma */ #define HW_GBYBIT WNVHW_GBYBIT /* Video Input Gray to Binary on Luma */ #define HW_VSPBIT WNVHW_VSPBIT /* Video Input VSP Enable */ #define HW_VSDBIT WNVHW_VSDBIT /* Video Input VSD Detect, Read Only */ // Video Contrast Reg #define HW_VCTCRFIELD WNVHW_VCTCRFIELD /* Cr contrast */ #define HW_VCTCBFIELD WNVHW_VCTCBFIELD /* Cb Contrast */ #define HW_VCTYFIELD WNVHW_VCTYFIELD /* Y Contrast */ #define HW_VHSDFIELD WNVHW_VHSDFIELD /* Video Horizontal Synch Delay */ // Control-L Reg #define HW_STRBIT WNVHW_STRBIT /* Control-L Start bit */ #define HW_TRGBIT WNVHW_TRGBIT /* Control-L Trigger Send */ #define HW_ARMBIT WNVHW_ARMBIT /* Control-L Armed, Read Only */ #define HW_VVSBIT WNVHW_VVSBIT /* Video Vert Synch, Read Only */ #define HW_CLDBIT WNVHW_CLDBIT /* Control-L Direct Data */ #define HW_E2BIT WNVHW_E2BIT /* TBD */ #define HW_E1BIT WNVHW_E1BIT /* TBD */ #define HW_E0BIT WNVHW_E0BIT /* TBD */ #define HW_CLDATA WNVHW_CLDATA /* Control L Data */ #else // W95/NT #include "caviario.h" #define HW_PORT_HST1PTR CIO_HST1PTR #define HW_PORT_HST2PTR CIO_HST2PTR #define HW_PORT_SPLPTR CIO_SPLPTR #define HW_PORT_AUDPTR CIO_AUDPTR #define HW_PORT_VID1PTR CIO_VID1PTR #define HW_PORT_MXRPTR CIO_MXRPTR #define HW_PORT_VID2PTR CIO_VID2PTR #define HW_PORT_MXWPTR CIO_MXWPTR #define HW_PORT_HST1DAT CIO_HST1DAT #define HW_PORT_HST2DAT CIO_HST2DAT #define HW_PORT_RLDPTR1 CIO_RLDPTR1 #define HW_PORT_RLDPTR2 CIO_RLDPTR2 #define HW_PORT_MMA CIO_MMA #define HW_PORT_CTL CIO_CTL #define HW_PORT_ISR CIO_ISR #define HW_PORT_ITR CIO_ITR #define HW_PORT_ATTN CIO_ATTN #define HW_PORT_GAIN CIO_GAIN #define HW_PORT_FREQ CIO_FREQ #define HW_PORT_4C00 CIO_4C00 #define HW_PORT_AUDMIX1 CIO_AUDMIX1 #define HW_PORT_AUDMIX2 CIO_AUDMIX2 #define HW_PORT_5800 CIO_5800 #define HW_PORT_5C00 CIO_5C00 #define HW_PORT_VOF CIO_VOF #define HW_PORT_VCT CIO_VCT #define HW_PORT_6800 CIO_6800 #define HW_PORT_CTL2 CIO_CTL2 #define HW_PORT_6C00 CIO_6C00 #define HW_PORT_CTLL CIO_CTLL #define HW_PORT_7400 CIO_7400 #define HW_PORT_BANKSEL CIO_BANKSEL #define HW_PORT_7800 CIO_7800 #define HW_PORT_I2C CIO_I2C #define HW_PORT_TSTMODE CIO_TSTMODE // MMA Register #define HW_NWDBIT CIO_NWDBIT /* NOWS Write Disable */ #define HW_NRDBIT CIO_NRDBIT /* NOWS Read Disable */ #define HW_MMAFIELD CIO_MMAFIELD /* Memory Map Address */ #define HW_MMEBIT CIO_MMEBIT /* Memory Map Enable */ #define HW_FMFIELD CIO_FMFIELD /* FM config, Read only */ #define HW_DSSFIELD CIO_DSSFIELD /* Disney Sound Source config, Read Only */ #define HW_CVXFIELD CIO_CVXFIELD /* CoVoX speech thing config, Read Only */ #define HW_REVFIELD CIO_REVFIELD /* WAVIA ASIC Revision, Read Only */ #define HW_AVGCENBIT CIO_AVGCENBIT /* W97 and later: Average Chroma Enable */ #define HW_AUDXSEL_INT97 CIO_AUDXSEL_INT97 /* W97: Crystal selection is internal (using IMI bit) */ #define HW_AUDXSEL CIO_AUDXSEL /* WIMP: Crystal selection (replaces IMI bit) */ #define HW_CS4218BIT CIO_CS4218BIT /* W97 and later: 4218 codec configuration */ #define HW_VDECODESEL CIO_VDECODESEL /* W97 and later: Video decoder select for inverted polarity */ #define HW_BANKSEL CIO_BANKSEL /* W97 and later: to enable the memory chip select */ #define HW_DHYYY CIO_DHYYY /* W97 and later: Luma only Delta Huffman */ #define HW_DHRES CIO_DHRES /* W97 and later: Delta Huffman Residual alogorithm */ #define HW_DHRND CIO_DHRND /* W97 and later: Delta Huffman Rounding algorithm */ #define HW_MEDREN CIO_MEDREN /* W97 and later: Median Filter Return Effect */ #define HW_VIDVCI CIO_VIDVCI /* W97 and later: DVCI video format */ #define HW_VERSIONFIELD CIO_VERSIONFIELD /* W95 and later: Read Only Version */ #define HW_WAVIIDFIELD CIO_WAVIIDFIELD /* All Versions: WAVI ASIC Revision, Read Only */ #define HW_FULLID CIO_FULLID /* completely identify the chip version... W95 and above! */ // // Chip identification in MMA #define HW_CHIP_ID_MASK CIO_FULLID #define HW_WAVI1 CIO_WAVI1 /* The original Samsung */ #define HW_WAVI95 CIO_WAVI95 /* Hundai part with line avg during Huffman fix */ #define HW_WAVI97 CIO_WAVI97 #define HW_WIMP CIO_WIMP // CTL Register #define HW_VSEBIT CIO_VSEBIT /* Video Sampler Enable */ #define HW_VSTBIT CIO_VSTBIT /* Video Status */ #define HW_VSSBIT CIO_VSSBIT /* Video Source Select */ #define HW_VSCBIT CIO_VSCBIT /* Video Source Component(1)/Composite(0) */ #define HW_RGBBIT CIO_RGBBIT /* RGB(1)/YUV(0) Video Space */ #define HW_VFSFIELD CIO_VFSFIELD /* Video Filter Select */ #define HW_VFSFIELD_NONE CIO_VFSFIELD_NONE /* Bypass filters */ #define HW_VFSFIELD_MED3 CIO_VFSFIELD_MED3 /* 3 tap median filter */ #define HW_VFSFIELD_FIR2 CIO_VFSFIELD_FIR2 /* 2 pix FIR filter */ #define HW_VFSFIELD_BOTH2 CIO_VFSFIELD_BOTH2 /* Median and 2 pix FIR */ #define HW_VFSFIELD_MED4 CIO_VFSFIELD_MED4 /* 4 pix FIR filter */ #define HW_VFSFIELD_BOTH4 CIO_VFSFIELD_BOTH4 /* Median and 4 pix FIR */ #define HW_VFSFIELD_MED8 CIO_VFSFIELD_MED8 /* 8 pix FIR filter */ #define HW_VFSFIELD_BOTH8 CIO_VFSFIELD_BOTH8 /* Median and 8 pix FIR filter */ #define HW_VDFFIELD CIO_VDFFIELD /* Video Data Capture Format */ #define HW_VDFFIELD_DYCQ CIO_VDFFIELD_DYCQ /* DYCQ */ #define HW_VDFFIELD_YCQ CIO_VDFFIELD_YCQ /* YCQ */ #define HW_VDFFIELD_YCH CIO_VDFFIELD_YCH /* YCH */ #define HW_VDFFIELD_RGB CIO_VDFFIELD_RGB /* RGB */ #define HW_VDFFIELD_DH4 CIO_VDFFIELD_DH4 /* DH4 */ #define HW_VDFFIELD_DH5 CIO_VDFFIELD_DH5 /* DH5 */ #define HW_VDFFIELD_DH6 CIO_VDFFIELD_DH6 /* DH6 */ #define HW_VDFFIELD_DH7 CIO_VDFFIELD_DH7 /* DH7 */ #define HW_CTLBIT4 CIO_CTLBIT4 /* not used */ #define HW_I2CBIT CIO_I2CBIT /* I2C Bus Clock */ #define HW_IMIBIT CIO_IMIBIT /* IM-Bus Identify */ #define HW_IMCBIT CIO_IMCBIT /* IM-Bus Clock */ #define HW_IMDBIT CIO_IMDBIT /* IM-Bus Data */ /* WIMP variation */ #define HW_SCL CIO_SCL /* WIMP: I2C bus clock */ #define HW_PIXGEN CIO_PIXGEN /* WIMP: pixel generator */ #define HW_PXCCD CIO_PXCCD /* WIMP: Pixel Genreator CCD Mode enable */ #define HW_SDA CIO_SDA /* WIMP: I2C bus data */ // CTL2 Register (WIMP ONLY) #define HW_CCLKEN CIO_CCLKEN //Enable CCLK */ #define HW_VCLK_INV CIO_VCLK_INV //Invert VCLK */ #define HW_DPLL_EN CIO_DPLL_EN //Digital PLL enable */ #define HW_VCPHASE CIO_VCPHASE //Vclock Phase control */ #define HW_VCLK_EN CIO_VCLK_EN //Vclock source selection */ #define HW_VCLK_EN_GND CIO_VCLK_EN_GND //00 for ground */ #define HW_VCLK_EN_MOV2 CIO_VCLK_EN_MOV2 // Mclock/2 */ #define HW_VCLK_EN_VEXT CIO_VCLK_EN_VEXT // External Vclock */ #define HW_VCLK_EN_MCLK CIO_VCLK_EN_MCLK // MClock */ #define HW_MCLK_EN CIO_MCLK_EN //Mclock source selection */ #define HW_MCLK_EN_GND CIO_MCLK_EN_GND //00 for ground */ #define HW_MCLK_EN_GND2 CIO_MCLK_EN_GND2 //00 for ground (reversed already!) */ #define HW_MCLK_EN_COV2 CIO_MCLK_EN_COV2 // CCD clock/2 */ #define HW_MCLK_EN_AUD CIO_MCLK_EN_AUD // Audio clock */ #define HW_MCLK_EN_CCLK CIO_MCLK_EN_CCLK // CCD Clock */ #define HW_GPIO2_OE CIO_GPIO2_OE //GPIO 2 OE */ #define HW_GPIO1_OE CIO_GPIO1_OE //GPIO 1 OE */ #define HW_GPIO0_OE CIO_GPIO0_OE //GPIO 0 OE */ #define HW_GPIO4 CIO_GPIO4 //GPIO 4 = RST_OUT */ #define HW_GPIO3 CIO_GPIO3 //GPIO 3 */ #define HW_GPIO2 CIO_GPIO2 //GPIO 2 */ #define HW_GPIO1 CIO_GPIO1 //GPIO 1 */ #define HW_GPIO0 CIO_GPIO0 //GPIO 0 */ // Interrupt register ISR/ITR bit mask #define HW_VIEBIT CIO_VIEBIT /* Video Interrupt Enable */ #define HW_VI2BIT CIO_VI2BIT /* Video Interrupt 1, Read Only */ #define HW_VI1BIT CIO_VI1BIT /* Video Interrupt 2, Read Only */ #define HW_AIEBIT CIO_AIEBIT /* Audio Interrupt Enable */ #define HW_AISFIELD CIO_AISFIELD /* Audio Interrupt Status, Read Only */ #define HW_AISFIELD_NOINT CIO_AISFIELD_NOINT /* no audio interrupt */ #define HW_AISFIELD_1INT CIO_AISFIELD_1INT /* one audio interrupt */ #define HW_AISFIELD_OVERRUN CIO_AISFIELD_OVERRUN /* audio overrun */ #define HW_AISFIELD_2INT CIO_AISFIELD_2INT /* two audio interrupts */ #define HW_FIEBIT CIO_FIEBIT /* FM Interrupt Enable */ #define HW_FMIBIT CIO_FMIBIT /* FM Interrupt, Read Only */ #define HW_SIEBIT CIO_SIEBIT /* SCSI Interrupt Enable */ #define HW_SCIBIT CIO_SCIBIT /* SCSI Controller Interrupt, Read Only */ #define HW_CIEBIT CIO_CIEBIT /* Control-L Interrupt Enable */ #define HW_CLIBIT CIO_CLIBIT /* Control-L Interrupt, Read Only */ #define HW_IDTBIT CIO_IDTBIT /* Interrupt Detect, Read Only */ #define HW_ITMBIT CIO_IDTBIT /* Interrupt test mode, Write Only */ #define HW_ISELFIELD CIO_ISELFIELD /* Interrupt Select */ #define HW_ISELFIELD_NONE CIO_ISELFIELD_NONE /* Interrupts disconnected */ #define HW_ISELFIELD_IRQ2 CIO_ISELFIELD_IRQ2 /* IRQ2 */ #define HW_ISELFIELD_IRQ5 CIO_ISELFIELD_IRQ5 /* IRQ5 was reversed with 7*/ #define HW_ISELFIELD_IRQ7 CIO_ISELFIELD_IRQ7 /* IRQ7 was reversed with 5 */ #define HW_ISELFIELD_IRQ10 CIO_ISELFIELD_IRQ10 /* IRQ10*/ #define HW_ISELFIELD_IRQ11 CIO_ISELFIELD_IRQ11 /* IRQ11*/ #define HW_ISELFIELD_IRQ12 CIO_ISELFIELD_IRQ12 /* IRQ12*/ #define HW_ISELFIELD_IRQ15 CIO_ISELFIELD_IRQ15 /* IRQ15*/ // Audio ATTN // 4216 (and ASCO) format of the upper 12 bits: #define HW_ATTN_MASK CIO_ATTN_MASK /* mask of useable bits */ #define HW_UNUSEDFIELD CIO_UNUSEDFIELD /* not used */ #define HW_ATTLFFIELD CIO_ATTLFFIELD /* Left Output Channel Attenuation, Write Only */ #define HW_ATTRTFIELD CIO_ATTRTFIELD /* Right Output Channel Attenuation, Write Only */ // 4218 format of the upper 12 bits: #define HW_4218_ATTLFFIELD CIO_4218_ATTLFFIELD /* 4218: 5 bit Left Output Channel Attenuation, Write Only */ #define HW_4218_ATTRTFIELD CIO_4218_ATTRTFIELD /* 4218: 5 bit Right Output Channel Attenuation, Write Only */ // common between 4216 and 4218 #define HW_ASS2FIELD CIO_ASS2FIELD /* Audio Source Select, Write Only */ #define HW_ASS2FIELD_VID1 CIO_ASS2FIELD_VID1 #define HW_ASS2FIELD_MIC CIO_ASS2FIELD_MIC #define HW_ASS2FIELD_VID2 CIO_ASS2FIELD_VID2 #define HW_ASS2FIELD_LINE CIO_ASS2FIELD_LINE #define HW_AFSBIT CIO_AFSBIT /* Audio freq select (SPAM only) 0=22.5792,1=24.576 */ #define HW_AXEBIT CIO_AXEBIT /* Audio expansion enable */ // Audio GAIN #define HW_MUTBIT CIO_MUTBIT /* Mute, Write Only */ #define HW_ISLBIT CIO_ISLBIT /* Input Select Left channel, Write Only */ /* 0=LIN1, 1=IN2 (ASS2) */ #define HW_ISRBIT CIO_ISRBIT /* Input Select Right channel, Write Only */ /* 0=LIN1, 1=IN2 (ASS2) */ #define HW_GAINLFFIELD CIO_GAINLFFIELD /* Left Input Channel Gain, Write Only */ #define HW_GAINRTFIELD CIO_GAINRTFIELD /* Right Input Channel Gain, Write Only */ // Audio FREQ #define HW_AOVFIELD CIO_AOVFIELD /* Audio Output Volume */ #define HW_ACEBIT CIO_ACEBIT /* Audio Converter Enable */ #define HW_APEBIT CIO_APEBIT /* Audio Phase Error */ #define HW_AMSBIT CIO_AMSBIT /* Audio Mode Stereo */ #define HW_ADDBIT CIO_ADDBIT /* Audio Digital Port Data */ #define HW_FREQFIELD CIO_FREQFIELD /* Audio Frequency */ #define HW_FREQFIELD_44100 CIO_FREQFIELD_44100 #define HW_FREQFIELD_29400 CIO_FREQFIELD_29400 #define HW_FREQFIELD_22050 CIO_FREQFIELD_22050 #define HW_FREQFIELD_14700 CIO_FREQFIELD_14700 #define HW_FREQFIELD_11025 CIO_FREQFIELD_11025 #define HW_FREQFIELD_08820 CIO_FREQFIELD_08820 #define HW_FREQFIELD_07350 CIO_FREQFIELD_07350 // Audio MIX 1/2 #define HW_MIXRFIELD CIO_MIXRFIELD /* Right channel output volume */ #define HW_MIXLFIELD CIO_MIXLFIELD /* Left channel output volume */ // Video Offset #define HW_VOFCRFIELD CIO_VOFCRFIELD /* Video Offset Chroma Red */ #define HW_VOFCBFIELD CIO_VOFCBFIELD /* Video Offset Chroma Blue */ #define HW_VOFYFIELD CIO_VOFYFIELD /* Video Offset Luma */ #define HW_GBCBIT CIO_GBCBIT /* Video Input Gray to Binary on Chroma */ #define HW_GBYBIT CIO_GBYBIT /* Video Input Gray to Binary on Luma */ #define HW_VSPBIT CIO_VSPBIT /* Video Input VSP Enable */ #define HW_VSDBIT CIO_VSDBIT /* Video Input VSD Detect, Read Only */ // Video Contrast Reg #define HW_VCTCRFIELD CIO_VCTCRFIELD /* Cr contrast */ #define HW_VCTCBFIELD CIO_VCTCBFIELD /* Cb Contrast */ #define HW_VCTYFIELD CIO_VCTYFIELD /* Y Contrast */ #define HW_VHSDFIELD CIO_VHSDFIELD /* Video Horizontal Synch Delay */ // Control-L Reg #define HW_STRBIT CIO_STRBIT /* Control-L Start bit */ #define HW_TRGBIT CIO_TRGBIT /* Control-L Trigger Send */ #define HW_ARMBIT CIO_ARMBIT /* Control-L Armed, Read Only */ #define HW_VVSBIT CIO_VVSBIT /* Video Vert Synch, Read Only */ #define HW_CLDBIT CIO_CLDBIT /* Control-L Direct Data */ #define HW_E2BIT CIO_E2BIT /* TBD */ #define HW_E1BIT CIO_E1BIT /* TBD */ #define HW_E0BIT CIO_E0BIT /* TBD */ #define HW_CLDATA CIO_CLDATA /* Control L Data */ #endif #endif